CSEM’s RISC-V expertise is the result from extensive and early participation in the RISC-V community and developing SoCs with RISC-V.
As one of the first members of RISC-V International, CSEM has been participating in workgroups and contributed to the trace and debug specification.
CSEM has also done a number of projects using RISC-V processors, one of which is the customization of a processor to reduce the power consumption so that it can be implemented in an autonomously powered wireless wearable device. The project resulted in an industry grade core with 3.2 CoreMark/MHz and 2.23uW/MHz in a 22nm process.
RISC-V is an open standard instruction set architecture (ISA), which is quickly gaining popularity and is now a viable alternative for ARM, certainly in low power applications, such as Edge computing and IoT.
The benefit of the RISC-V open standard is that companies implementing processors on their SoCs have much more freedom to decide whether they develop in-house, use open source, or buy proprietary cores, and have a much wider range of support/service models and possibilities for customizations than is the case in other ISA eco-systems. RISC-V has reduced significantly the problem of 'Vendor lock-in', and open-source implementations have even eliminated this process completely.
CSEM supports a wide range of processors from ultra-low power 32bit to high-performance 64bit processors
Other on request.
Choose CSEM as your partner for projects that demand quick time-to-market.
Whether you're: Integrating a processor into your SoC for the first time, transitioning smoothly from another ISA ecosystem to RISC-V, or tackling stringent low-power requirements.
CSEM has the expertise to drive your success.